Job title: PDK Engineer
Job type: Permanent
Emp type: Full-time
Industry: Engineering
Expertise: Engineering
Location: Federal Territory of Kuala Lumpur, Malaysia
Job published: 2021-09-06
Job ID: 32816

Job Description

RESPONSIBILITIES:

Process Design Kit (PDK) development group focuses on using the Technology Design Rules to develop, test and deploy design kits, for use in designing Analog and Digital ICs using the Cadence IC design tools. The goal is to improve design efficiency and productivity of design teams, and reduce design cycle time. The PDK Development Engineer will focus on the PDK development including Verification Rules writing (DRC, LVS, XRC, Antenna, Metal Fill, and ERC. EMI and IR Drop).

 

JOB DESCRIPTION/OTHER RECRUIREMENT:

Process Design Kit (PDK) development group focuses on using the Technology Design Rules to develop, test and deploy design kits, for use in designing Analog and Digital ICs using the Cadence IC design tools. The goal is to improve design efficiency and productivity of design teams, and reduce design cycle time.

  • Development of new techfiles and LEF, upgrade and maintenance of existing ones.
  • Development of new devices, enhancement of existing ones (CDF, Pcells and Callbacks code). ·
  • Development, enhancement and maintenance of DRC, LVS, and extraction rule files.
  • Validation of all components of PDK (complete front-end device, simulation, p-cell to backend physical design verification). ·
  • Maintenance and upgrade of existing views for supported tools. ·
  • Create and maintain PDK documentation. ·
  • Libraries characterization and Libraries validation. ·
  • Libraries views creation (front-end and back-end). ·
  • Maintenance and QA of existing libraries. ·
  • Development of libraries and IOs layouts.
  • Create and maintain libraries documentation. ·
  • Libraries packaging, installation and releases. Maintenance of associated scripts.

REQUIREMENT 

  • Minimum 1-5 years of experience in PDK development & validation. ·
  • Knowledge of front-to-back IC design flow. ·
  • Experience with Cadence IC Design tools. ·
  • Good technical ability to understand Design Rules Manual (DRM). ·
  • Experience in Custom physical Layout. ·
  • Experience in Calibre SVRF / DRC & LVS coding. ·
  • Proficiency in Cadence SKILL, Perl, UNIX, Shell and TLC/TL scripting languages.
  • Experience in standard cell libraries preferred. ·
  • Experience working with Place and Route tools is a plus. ·
  • Experience with parasitic extraction and simulation is a plus. ·
  • Good communication skills. ·
  • Demonstrate good documentation skills. ·
  • Able to work in a team environment.

AUTHORITY:

  • Authority to approve leave applications of supervisees ·
  • Authority to endorse monthly claim of supervisees

FOR ASSOCIATE PRINCIPAL ENGINEER AND ABOVE:

  • Minimum 5+ years’ of experience in PDK development