Job title: PnR - Lead role
Job type: Permanent
Emp type: Full-time
Industry: Engineering
Expertise: Engineering
Location: Federal Territory of Kuala Lumpur, Malaysia
Job published: 2021-09-06
Job ID: 32815

Job Description


  • BSEE/MSEE, with 7+ years of experience in large VLSI physical design implementation.
  • Implementation of multimillion gate designs in cutting edge process technologies (14nm, 10nm, 7nm, 5nm).
  • Strong hands-on experience in all aspects of physical design including synthesis, floor planning, place and route, clock tree synthesis, IP integration, extraction, timing closure, static timing analysis, power and signal integrity analysis, IR drop analysis, physical verification, DFM, ECO implementation and tapeout.
  • Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
  • Clear understanding and command over all aspects of physical design.
  • Experience with backend design tools such as Cadence Virtuoso, Cadence Soc Encounte/Innovusr, Mentor Graphics, Mentor Olympus-SoC, Synopsys IC Compiler, Calibre, etc.



Work closely with front end design engineers to translate RTL-to-GDSII and ensure successful tapeouts. Responsible for all aspects of physical design and implementation. Participating in or leading next generation physical design methodology, flow development and automation. Design responsibility includes synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management. Monitor and ensure all PnR projects meet project quality and milestones. Participate in PnR team schedule plans, hiring plans, including candidate interviews and recommendations for the growing team. Mentor less experienced engineers.

  • Successful track record of delivering products to production.
  • Coding in scripting languages such as Perl, Tcl, and UNIX shell, etc.
  • Knowledge of Verilog, LEF, DEF, GDS, DSPF, SDF, SDC and Liberty formats.
  • Self-motivated, able to work independently or as a team leader/team player.
  • Good verbal and writing communication skills.
  • Experience in low-power design techniques.

Strong problem solving ability.

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