Job title: PnR - Senior role
Job type: Permanent
Emp type: Full-time
Industry: Engineering
Expertise: Engineering
Location: Federal Territory of Kuala Lumpur, Malaysia
Job published: 2021-09-06
Job ID: 32813

Job Description

RESPONSIBILITIES:

Work closely with front end design engineers to translate RTL-to-GDSII.  Responsible for all aspects of physical design and implementation. Participate in the efforts of establishing physical design methodologies and flow automation. Work on chip and block floorplan, power/ clock distribution, chip assembly, P&R, and timing closure. Implement and monitor Quality Assurance/Quality Control standards based on corporate guidelines in a project setting. Train/mentor new employees. 

REQUIREMENTS:

  • At least 4-7 years professional experience in microelectronics physical implementation.
  • Successful track record of delivering products to production.
  • Coding in scripting languages such as Perl, Tcl, and UNIX shell, etc.
  • Knowledge of Verilog, LEF, DEF, GDS, DSPF, SDF, SDC and Liberty formats.
  • Good verbal and writing communication skills. · Fabrication process variation impacts and performance. ·
  • Experience in low-power design techniques.
  • Good understanding of ERC, EMI rules and impact on final chip verification and cycle time reduction.
  • Strong problem solving ability.
  • Ability to work in a team environment and participate in cross-functional activities.
  • Must be willing to travel for more than 6 months assignments abroad
  • Able to converse in Japanese and Chinese language are plus points
  • Experience with backend design tools such as Cadence Virtuoso, Cadence Soc Encounter/Innovus, Mentor Graphics, Mentor Olympus-SoC, Synopsys IC Compiler, Calibre, etc.

 

JOB DESCRIPTION/OTHER RECRUIREMENT:

  • Power planning, optimization, power grid and signal routing considering timing constraints. ·
  • Design floor planning, analogue and memory macro placement. ·
  • Place and route including timing closure.
  • Extraction of layout parasitics and SPEF/ SDF generation. Signal integrity tests.
  • Post-synthesis static timing analysis (STA) and post-layout STA. ·
  • Physical verification (DRC, ERC, LVS, ANTENNA rules). ·
  • Writing, running, optimization of scripts for above tasks. ·
  • Implement and monitor Quality Assurance/ Quality Control standards based on corporate guidelines in a project setting. ·
  • Have done multiple tape outs and proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.
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